// OK, let's begin:)



.section .init, "ax"
.code 32

.globl _start
_start:
	b		reset
	ldr		pc, _vector_undef
	ldr		pc, _vector_swi
	ldr		pc, _vector_pabt
	ldr		pc, _vector_dabt
	ldr		pc, _vector_resv
	ldr		pc, _vector_irq
	ldr		pc, _vector_fiq

_vector_undef:	.word vector_undef
_vector_swi:	.word vector_swi
_vector_pabt:	.word vector_pabt
_vector_dabt:	.word vector_dabt
_vector_resv:	.word vector_resv
_vector_irq:	.word vector_irq
_vector_fiq:	.word vector_fiq

/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */
/* exception handlers  */
	
//lgg , take care of lr , otherwise the fun will not return correct
vector_undef:
	stmfd R13!,{R0-R12,LR}
	mrs r4, spsr
	stmfd r13!,{r4}
	bl		rt_hw_trap_undef
	ldmfd r13!,{r4}
	msr SPSR_cxsf, r4
	ldmfd r13!,{r0-r12, pc}^

vector_swi:
	//sub lr, lr, #4  //sometime need this
	//   ;prevent interupt qiantao
	stmfd R13!,{R0-R12,LR}
	mrs r4, spsr
	stmfd r13!,{r4}
	bl rt_hw_trap_swi
	ldmfd r13!,{r4}
	msr SPSR_cxsf, r4
	ldmfd r13!,{r0-r12, pc}^

vector_pabt:
	stmfd R13!,{R0-R12,LR}
	mrs r4, spsr
	stmfd r13!,{r4}
	bl 		rt_hw_trap_pabt
	ldmfd r13!,{r4}
	msr SPSR_cxsf, r4
	ldmfd r13!,{r0-r12, pc}^

vector_dabt:
	stmfd R13!,{R0-R12,LR}
	mrs r4, spsr
	stmfd r13!,{r4}
	bl 		rt_hw_trap_dabt
	ldmfd r13!,{r4}
	msr SPSR_cxsf, r4
	ldmfd r13!,{r0-r12, pc}^
	
vector_resv:
	stmfd R13!,{R0-R12,LR}
	mrs r4, spsr
	stmfd r13!,{r4}
	bl 		rt_hw_trap_resv
	ldmfd r13!,{r4}
	msr SPSR_cxsf, r4
	ldmfd r13!,{r0-r12, pc}^

vector_irq:
	stmfd R13!,{R0-R12,LR}
	mrs r4, spsr
	stmfd r13!,{r4}
	bl 		rt_hw_trap_irq
	ldmfd r13!,{r4}
	msr SPSR_cxsf, r4
	ldmfd r13!,{r0-r12, pc}^

vector_fiq:
	stmfd R13!,{R0-R12,LR}
	mrs r4, spsr
	stmfd r13!,{r4}
	bl 		rt_hw_trap_fiq
	ldmfd r13!,{r4}
	msr SPSR_cxsf, r4
	ldmfd r13!,{r0-r12, pc}^

//**************************************
// 1.disabble Watch dog                *
//**************************************	
reset:
disabble_watch_dog:
	mov r1,#0x53000000
	mov r2,#0x0
	str r2,[r1]


//**************************************
// 2.disabble Interrupt                *
//**************************************

disablle_interrupt:
	ldr r1,=0x4a000008
	mov r2,#0x0
	str r2,[r1]
	
//**************************************
// 3.clock set FCLK=304MHz             *
//   FCLK:HCLK:PCLK = 6:3:1            *   
//   UCLK = 48MHz                      *
//**************************************
	
clock_set:

//MMU_setAsyncBusMode  
	mrc p15,0,r1,c1,c0,0
	orr r1,r1,#0xc0000000
	mcr p15,0,r1,c1,c0,0
	
	//CAMDIVN
	ldr r0,=0x4c000018
	mov r1,#0x0
	str r1,[r0]
	
	
	//LOCKTIME PLL
	ldr r0,=0x4c000000
	ldr r1,=0x00ffffff
	str r1,[r0]
	
	//UPLLCON
	ldr r0,=0x4c000008
	ldr r1,=0x00038022
	str r1,[r0]
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	
	//MPLLCON
	ldr r0,=0x4c000004
	ldr r1,=0x00044011
	str r1,[r0]
	
	//CLKCON
	ldr r0,=0x4c00000c
	ldr r1,=0x00fffff0
	str r1,[r0]
	
	//CLKSLOW
	ldr r0,=0x4c000010
	ldr r1,=0x00000004
	str r1,[r0]
	
	//CLKDIVN
	ldr r0,=0x4c000014
	ldr r1,=0x00000007
	str r1,[r0]

//**************************************
// 4.Init sdram                        *
//**************************************
/*
memsetup:
	ldr r1,=MEM_CTL_BASE  
	adrl r2,mem_cfg_val   
	add r3,r1,#52
memsetup_1:
	ldr r4,[r2],#4
	str r4,[r1],#4
	cmp r1,r3
	bne memsetup_1
	nop
	nop
	nop
	nop

.equ 	MEM_CTL_BASE,  0X48000000

mem_cfg_val:
	DCD 0x22111110
	DCD 0x00000700
	DCD 0x00000700
	DCD 0x00000700
	DCD 0x00000700
	DCD 0x00000700
	DCD 0x00000700
	DCD 0X00018005
	DCD 0X00018005
	DCD 0X008E0459
	DCD 0X000000B1
	DCD 0X00000030
	DCD 0X00000030
*/
	
//**************************************
// 5.set ram stack for C app           *
//**************************************	
	/* change to user mode */
	mov r0, #0xd0
	MSR CPSR_cxsf, r0

.globl c_entry
	ldr sp, =0x33ef0000

	b c_entry
